Evolution of Test Programs Exploiting a FSM Processor Model

Microprocessor testing is becoming a challenging task, due to the increasing complexity of modern architectures. Nowadays, most architectures are tackled with a combination of scan chains and Software-Based Self-Test (SBST) methodologies. Among SBST techniques, evolutionary feedback-based ones prove effective in microprocessor testing: their main disadvantage, however, is the considerable time required to generate suitable test programs. A novel evolutionary-based approach, able to appreciably reduce the generation time, is presented. The proposed method exploits a high-level representation of the architecture under test and a dynamically built Finite State Machine (FSM) model to assess fault coverage without resorting to time-expensive simulations on low-level models. Experimental results, performed on an OpenRISC processor, show that the resulting test obtains a nearly complete fault coverage against the targeted fault mode

Low-Cost On-Chip Clock Jitter Measurement Scheme

In this paper, we present a low-cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in situ jitter measurement during the test or debug phase. It provides very high measurement resolution and accuracy, despite the possible presence of power supply noise (representing a major source of clock jitter), at low area and power costs. The achieved resolution is scalable with technology node and can in principle be increased as much as desired, at low additional costs in terms of area overhead and power consumption. We show that, for the case of high performance microprocessors employing ring oscillators (ROs) to measure process parameter variations (PPVs), our jitter measurement scheme can be implemented by reusing part of such ROs, thus allowing to measure clock jitter with a very limited cost increase compared with PPV measurement only, and with no impact on parameter variation measurement resolution

Cosmic Acceleration in Brans-Dicke Cosmology

We consider Brans-Dicke theory with a self-interacting potential in Einstein conformal frame. We show that an accelerating expansion is possible in a spatially flat universe for large values of the Brans-Dicke parameter consistent with local gravity experiments.Comment: 10 Pages, 3 figures, To appear in General Relativity and Gravitatio

Discovery of widespread transcription initiation at microsatellites predictable by sequence-based deep neural network

Using the Cap Analysis of Gene Expression (CAGE) technology, the FANTOM5 consortium provided one of the most comprehensive maps of transcription start sites (TSSs) in several species. Strikingly, ~72% of them could not be assigned to a specific gene and initiate at unconventional regions, outside promoters or enhancers. Here, we probe these unassigned TSSs and show that, in all species studied, a significant fraction of CAGE peaks initiate at microsatellites, also called short tandem repeats (STRs). To confirm this transcription, we develop Cap Trap RNA-seq, a technology which combines cap trapping and long read MinION sequencing. We train sequence-based deep learning models able to predict CAGE signal at STRs with high accuracy. These models unveil the importance of STR surrounding sequences not only to distinguish STR classes, but also to predict the level of transcription initiation. Importantly, genetic variants linked to human diseases are preferentially found at STRs with high transcription initiation level, supporting the biological and clinical relevance of transcription initiation at STRs. Together, our results extend the repertoire of non-coding transcription associated with DNA tandem repeats and complexify STR polymorphism

Won’t On-Chip Clock Calibration Guarantee Performance Boost and Product Quality ?

In today's high performance (multi-GHz) microprocessors' design, on-chip clock calibration features are needed to compensate for electrical parameter variations as a result of manufacturing process variations. The calibration features allow performance boost after manufacturing test and maintain such performance levels during normal operation, thus preserving product quality. This strategy has been proven successful commercially. In this paper, we discuss the impact on performance and product quality of both permanent and transient faults possibly affecting these calibration circuits during manufacturing and normal operation, respectively. In particular, we consider the case of an on-chip clock calibration feature of a commercial high performance microprocessor. We show that some possible permanent faults may render the on-chip clock calibration schemes useless (in process variations' compensation), while it is impossible for common manufacturing testing to detect this incorrect behavior. This means that a faulty operating microprocessor may pass the testing phase and be put onto the market, with a consequent impact on product quality and increase in defect level. Similarly, we show that some possible transient faults occurring during the microprocessor in-field operation could defeat the purpose of on-chip clock calibration, again resulting in faulty operation of the microprocessor. This has long range implications to microprocessors' design as well, considering that process variations on die, as well as across the process, would worsen with continued scaling. Proper strategies to test these clock calibration features and to guarantee their correct operation in the field cannot be ignored. Possible design approaches to solve this problem are discussed

Clock calibration faults and their impact on quality of high performance microprocessors

In this paper we analyze the fault effects of some clock calibration features which are common to today's high performance microprocessors. We show that induced faults with such schemes may give rise to effects that are not detectable by common manufacturing testing (e.g. scan based). However, these faults could seriously impact the microprocessor correct operation, and result in a decrease of product quality. Similar considerations may apply to different microprocessor calibration features. Considering that there is a wide range of process variations on die, as well as across the process, and that very deep sub-micron circuits tend to provide higher levels of performance to the circuits, the use of such on-die calibration features will increase in all segments of design. Proper strategies to test these features cannot be ignore

13th IEEE International on-line testing symposium

13th IEEE International On-Line Testing Symposium The 13th IEEE International On-Line Testing Symposium took place on 8-11 July 2007 in Crete, Greece. The IOLTS 07 technical program began with a TTTC Test Technology Educational Program (TTEP) full-day tutorial. There were also three excellent keynotes. The technical program included a regular track of 11 paper sessions (with 33 technical papers) and an interactive poster session, as well as three special sessions. © 2007 IEEE

Finite element modeling of contact interface between trans-tibial residual limb and prosthetic socket

Finite element method has been identified as a useful tool to understand the load transfer mechanics between a residual limb and its prosthetic socket. This paper proposed a new practical approach in modeling the contact interface with consideration of the friction/slip conditions and pre-stresses applied on the limb within a rectified socket. The residual limb and socket were modeled as two separate structures and their interactions were simulated using automated contact methods. Some regions of the limb penetrated into the socket because of socket modification. In the first step of the simulation, the penetrated limb surface was moved onto the inner surface of the socket and the pre-stresses were predicted. In the subsequent loading step, pre-stresses were kept and loadings were applied at the knee joint to simulate the loading during the stance phase of gait. Comparisons were made between the model using the proposed approach and the model having an assumption that the shape of the limb and the socket were the same which ignored pre-stress. It was found that peak normal and shear stresses over the regions where socket undercuts were made reduced and the stress values over other regions raised in the model having the simplifying assumption

Novel On-Chip Clock Jitter Measurement Scheme For High Performance Microprocessors

In this paper we present an on-chip clock jitter digital measurement scheme for high performance microprocessors. The scheme enables in-situ jitter measurement of the clock distribution network during the test or the debug phase. It provides very high measurement resolution, despite the possible presence of power supply noise (constituting a major cause of clock jitter) affecting itself. The resolution is higher than a min sized inverter input-output delay, and can on principle be further increased, at some additional costs in terms of area overhead and power consumption. In this paper, a resolution of the 1.8% of the clock period is achieved with limited area and power costs